The present invention relates to a technique for inspection of fine circuit patterns on circuit boards for semiconductor devices, liquid crystal displays, and the like, by use of an electron beams.
As an example of the currently available processing, a typical method of inspecting a fine circuit pattern on a wafer (board) will be described.
An integrated circuit is performed by printing patterns, which are formed on photo masks, on a wafer successively by lithography and etching. The yield of ICs produced in this way is affected by errors in the printing patterns, the entry of foreign matters, etc; accordingly, patterns on wafers are inspected in the course of manufacture of the ICs.
Defects of circuit patterns on wafers are mainly detected optically or by using an electron beam. With patterns becoming ever finer and more complex, the shapes becoming ever more complex, and the materials becoming more diversified, it has become more difficult to detect defects by use of optical methods. Under the circumstances, there have been proposed various methods of inspecting such patterns on the basis of their images as reproduced with electron beams, the resolution of which images is higher than that of optical images.
According to some methods that have been proposed, an electron beam is applied to a circuit board to obtain an image of its circuit pattern. When defects are detected, the images are stored and analyzed to determine the kinds of defects automatically (for example, see JP-A No. 160402/1999, referred to hereinafter as Patent Document 1).
As an example, a typical existing method of measuring the dimensions of a fine circuit pattern on a wafer will be described. As the circuit patterns of IC's become finer, more strict control of the dimensions and shapes of the circuit patterns on the wafers is required. In this regard, even slight dimensional errors affect the performance of the ICs.
Circuit patterns on wafers are measured optically or by using an electron beam. Electron beams are mainly used for the measurement of holes and the measurement of two-dimensional images. According to some methods that have been proposed, the top surface of the sample under inspection is charged with an electron beam and a first acceleration voltage, and then a second acceleration voltage is applied to the sample to obtain an image for observation (for example, see Patent Document 2: JP-A No. 200579/2000, referred to hereinafter as Patent Document 2).
As described above, with use of the technique for inspecting and measuring circuit patterns with electron beams, the quality control, such as the control of dimensions and the detection of defects, under a higher lateral resolution is possible.
The existing inspection apparatuses use a probe current of several tens of nanoamperes and an electron beam that is accelerated in the range from several hundred volts to ten kilovolts, which poses no problems so long as silicon oxide or the like is used for the insulating films between layers. With circuit patterns ever becoming finer and the data-processing speeds of ICs ever increasing, however, it is becoming essential to use porous low-permittivity materials.
Although Patent Documents 1 and 2 claim that the acceleration voltage of an electron beam against a wafer is variable in the range from several hundred volts to ten kilovolts (in the case of an inspection apparatus) and several tens of volts to two kilovolts (in the case of a length-measuring apparatus), they do not mention any technique for inspection and measurement that is capable of reducing damage to resists and porous low-permittivity materials.
As described above, the prior methods hardly address the problem of damage to circuit patterns that is caused by the exposure of the materials thereof to electron beams. Accordingly, when wafers with circuit patterns including resists and porous materials are inspected, the resists and porous materials are damaged and the dimensions of circuit patterns deviate from their design values.
The present inventor et al. have ascertained that when wafers including resists and porous materials are inspected by the existing methods, the following damage occurs to wafers.    (1) Materials are decomposed and shrink. Patterns on wafers change under the exposure to electron beams, and the reliability of measurement is reduced.    (2) Materials are decomposed by exposure to electron beams, which affects their characteristics, such as adhesion to other materials.
The above-described phenomena (1) and (2) lower the yield and the performance of ICs.